Modem ultra-large scale integrated (ULSI) circuits are constructed with up to several millions of active devices, such as transistors and capacitors, formed in a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polysilicon and metal, which are etched to form conductors for carrying signals between the various active devices. The individual interconnection layers are nominally electrically isolated from one another, and from the silicon substrate, by an insulating interlayer dielectric (ILD), such as silicon dioxide (SiO2) produced by chemical vapor deposition (CVD). The conductive layers and interlayer dielectric are deposited on the silicon substrate wafer in succession, with each layer being, for example, of the order of 1 micron in thickness. The ILD conformably covers the underlying layer (e.g. a metal layer etched to form conductive interconnects) such that the upper surface of the ILD is characterized by a series of non-planar steps which correspond in height and width to the underlying interconnect lines. The dielectric layer may also be an inter-metal interlevel dielectric (IMD) between an underlying metal interconnect layer and an ensuing overlying metal interconnect layer.
Height variations in the upper surface of a dielectric can have deleterious effects on the subsequent steps and layers applied in forming the integrated circuit. For example, a non-planar dielectric surface can interfere with the optical resolution of subsequent photolithographic processing steps. This can make the high resolution lines required for compact ULSI circuits difficult to produce. Additionally, if the height variations in the dielectic surface are severe, there is a danger that insufficient metal coverage can occur at the step height variations in the subsequent conductor layer, which can result in open circuit flaws.
Chemical Mechanical Polishing (CMP) is an industry recognized process for making the upper surface of a dielectric planar (i.e. planarization). This approach employs abrasive polishing to remove the surface height variations of the dielectric layer. The semiconductor wafer is pressed against a moving polishing surface that may be wetted with a chemically reactive, abrasive slurry. The polishing pad bridges over relatively low spots on the wafer, thus removing material from the relatively high spots on the wafer. Planarization occurs because high spots on the wafer polish faster than low spots on the wafer. Thus, the relatively high portions of the wafer are smoothed to a uniform level faster than the other, relatively low portions of the wafer.
Referring to FIG. 1, the CMP process is typically a four step procedure. The wafer is first subjected to an initial polish 10 for a certain amount of time to reduce the thickness of the layer. The length of the polishing time is estimated such that the thickness does not go below a targeted value. The resulting thickness of the layer is then measured 12. Using the measured thickness and the initial polishing time, the polish rate is calculated 14. Finally, the wafer is polished again for a time that is calculated to achieve the desired final thickness, based on the polish rate 16. This procedure has a number of disadvantages, mainly due to the manual estimations and calculations that are required. Inconsistent thickness targeting can lead to poor control of the process, and unacceptable wafers must be scrapped. Different dielectric layers require different polish times, making it difficult to run CMP processes in the manufacture of more than one type of wafer, for example, wafers having a nitride dielectric and wafers having an oxide dielectric. It is also very difficult to account for other parameters which affect CMP, such as incoming dielectric thickness, pattern density, removal rate, and pad hours. Thus, it is not possible to track the overall process to determine the source of errors and the resultant scrapping of unacceptable wafers.